
module  greedy_snake_top(
    input        sys_clk,
    input        sys_rst_n,
    input  [3:0] key,
    input  touch_key,


    output       hsync,
    output       vsync,
    output       vga_de,
    output [23:0] rgb
);

//wire define
wire          pixel_clk;
wire          clk_locked;



wire rst_n;

//*****************************************************
//**                    main code
//*****************************************************

assign rst_n = sys_rst_n & clk_locked;

//PLL
pll u_pll (
    .clkin1   (  sys_clk    ),//50MHz
    .clkout0  (  pixel_clk),//148.5M 1080P60
    .clkout1  (       ),//10MHz
    .clkout2  (      ),//25M
    .clkout3  (      ), // output
    .pll_lock (  clk_locked     )
);

top u_top(

    .rst_n          (rst_n),
    .key            (key),
    .touch_key      (touch_key),

    .vga_clk(pixel_clk),
    .vga_hsync       (hsync),
    .vga_vsync       (vsync),
    .vga_de       (vga_de),
    .vga_rgb      (rgb)
    );


endmodule 